The present invention relates to forward error correction decoding, and more specifically, to forward error correction decoding for a software radio system.
Wireless communication technology develops day by day. High computing capabilities, sufficient flexibility and scalability are not only development trends but also challenges confronting base station systems for next-generation wireless communication systems. For example, an Long Term Evolution (herein “LTE”) system requires high data throughput, such as 100 Mbps downlink and 50 Mbps uplink. Further, in an LTE system, part of the data (e.g., downlink broadcast channel BCH, downlink control information DCI, and par of uplink control information UCI) requires Viterbi decoding, whereas part of the data (e.g., uplink shared channel UL-SCH, downlink shared control channel DL-SCH, paging channel PCH, multicast channel MCH) requires Turbo decoding.
A traditional base station, especially a baseband processing portion therein, is mainly constructed based on various kinds of dedicated hardware designs and exhibits relatively poor flexibility and scalability. In order to be adapted to different standards and different application features supported by next-generation wireless communication systems, different models or amounts of dedicated chips need to be used in most cases, and further the hardware platform of a base station has to be re-developed. Hence, the traditional base station based on dedicated hardware designs can no longer satisfy requirements of a future wireless communication system.
In particular, physical layer processing usually occupies more than 80% of the total computation load of baseband processing of a base station, while forward error correction (FEC) decoding consumes more than 70% of the computation load of physical layer processing. For example, WiMAX Viterbi decoding usually requires single-threaded performance of 22.3 Mbps in case of 4-bit soft input decision, and WiMAX Turbo Code decoding requires single-threaded performance of 0.7 Mbps in case of six times of iterations. At present, the requirement for mass computation of FEC decoding processing is mainly solved by Application Specific Integrated Circuits (herein “ASIC”) techniques and chip sets. However, the dedicated hardware design based on ASIC techniques is rather poor in flexibility and scalability and thus fails to meet requirements of next-generation mobile communication. Common codec techniques in modern communication, including convolutional code, parity check code, Viterbi code, Turbo code, etc., belong to FEC code techniques. Hereinafter, encoding or decoding is referred to as FEC encoding or FEC decoding, unless otherwise specified.
In view of the foregoing problems, there is a need for a base station system suitable for a next-generation wireless communication system. Particularly, there is a need for an effective, flexible decoding solution suitable for such a base station system.